IST register fix

DSPWriter.cpp

@@ -54,18 +54,20 @@ bool DSPWriter::writeRegisterBlock(uint16_t subAddress, int dataLength, const ui
 
 void DSPWriter::writeRegister(uint16_t memoryAddress, uint8_t length, const uint8_t* data)
 {
+    if (memoryAddress == dspRegister::CoreRegister && length >= 2) {
+        s_coreRegCache[0] = data[0];
+        s_coreRegCache[1] = data[1];
+    }
+
     uint8_t LSByte = (uint8_t)memoryAddress & 0xFF;
     uint8_t MSByte = memoryAddress >> 8;
 
-    Wire.beginTransmission(DSP_I2C_ADDRESS); // Begin write
-
-    Wire.write(MSByte); // Send high address
-    Wire.write(LSByte); // Send low address
-
+    Wire.beginTransmission(DSP_I2C_ADDRESS);
+    Wire.write(MSByte);
+    Wire.write(LSByte);
     for (uint8_t i = 0; i < length; i++)
-        Wire.write(data[i]); // Send all bytes in passed array
-
-    Wire.endTransmission(); // Write out data to I2C and stop transmitting
+        Wire.write(data[i]);
+    Wire.endTransmission();
 }
 
 // ---------------------------------------------------------------
@@ -73,7 +75,9 @@ void DSPWriter::writeRegister(uint16_t memoryAddress, uint8_t length, const uint
 // instances, but exposed via resetSafeload() so the TCP bridge
 // can flush and reset cleanly on session start and disconnect.
 // ---------------------------------------------------------------
-static uint8_t s_safeload_count = 0;
+static uint8_t s_safeload_count   = 0;
+static uint8_t s_coreRegCache[2]  = {0x00, 0x00}; // last value written to CoreRegister
+static constexpr uint8_t IST_MASK = 0x3C;          // bits to OR in to trigger safeload IST
 
 void DSPWriter::resetSafeload()
 {
@@ -82,7 +86,7 @@ void DSPWriter::resetSafeload()
     // commits whatever is pending to parameter RAM so the DSP counter resets
     // to zero before the next session writes new safeload data.
     if (s_safeload_count > 0) {
-        uint8_t ist[2] = { 0x00, 0x3C };
+        uint8_t ist[2] = { s_coreRegCache[0], (uint8_t)(s_coreRegCache[1] | IST_MASK) };
         DSPWriter::writeRegister(dspRegister::CoreRegister, sizeof(ist), ist);
     }
     s_safeload_count = 0;
@@ -107,9 +111,8 @@ void DSPWriter::safeload_writeRegister(uint16_t memoryAddress, uint8_t* data, bo
 
     if (finished == true || s_safeload_count >= 5) // Max 5 safeload slots
     {
-        addr[0] = 0x00;
-        addr[1] = 0x3C; // IST bit — initiate safeload transfer
-        DSPWriter::writeRegister(dspRegister::CoreRegister, sizeof(addr), addr);
+        uint8_t ist[2] = { s_coreRegCache[0], (uint8_t)(s_coreRegCache[1] | IST_MASK) };
+        DSPWriter::writeRegister(dspRegister::CoreRegister, sizeof(ist), ist);
         s_safeload_count = 0;
     }
 }